AMD Zen 6 EPYC Venice pictured as 256-core chip with twin I/O dies

AMD’s next-generation Zen 6 architecture, codenamed “Venice,” is set to debut with a massive 256-core configuration, according to leaked images and reports. The chip is expected to feature two large I/O dies and will be the first high-performance computing (HPC) processor built on a 2-nanometer manufacturing process to enter volume production. This marks a significant leap in core counts and process technology for AMD’s server lineup.

The Zen 6 EPYC Venice processor is designed for data centers and cloud computing environments, targeting enterprises and hyperscalers that require extreme parallel processing power. The 256-core design, combined with the twin I/O dies, suggests a focus on high-bandwidth memory and I/O connectivity, which are critical for HPC workloads such as AI training, scientific simulations, and large-scale data analytics.

This development matters because it positions AMD to compete directly with Intel’s upcoming server chips and maintain its momentum in the server CPU market, where it has already captured a 46% share. The shift to a 2nm process node, likely manufactured by TSMC, promises significant improvements in performance per watt, potentially lowering operational costs for data centers. The 256-core count would more than double the core count of AMD’s current top-end EPYC Bergamo chips, which offer up to 128 cores.

According to leaked benchmarks, a 10-core Zen 6 engineering sample has already achieved a record single-core score on Geekbench, hinting at strong single-threaded performance alongside the massive multi-core capability. The same leaks indicate that Zen 6 EPYC CPUs will operate at frequencies exceeding 5 GHz, a notable achievement for a chip with such a high core count.

Background: AMD’s Zen architecture has steadily increased core counts with each generation, from 64 cores in Zen 2 to 128 in Zen 4c (Bergamo). The move to 2nm for Zen 6 represents a major process node jump from the 5nm used for Zen 4 and Zen 5. The Venice codename follows AMD’s tradition of using city names for EPYC generations.

Looking ahead, the Zen 6 EPYC Venice is expected to enter volume ramp in 2025 or 2026, with official announcements likely at AMD’s next major server launch event. The chip will face competition from Intel’s Granite Rapids and Sierra Forest processors, as well as Arm-based server chips from Ampere and others. The success of Venice could further solidify AMD’s server market share and drive adoption of 2nm technology in the HPC sector.